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5 Volt Intel(R) StrataFlashTM Memory
28F320J5 and 28F640J5 (x8/x16)
Preliminary Datasheet
Product Features
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High-Density Symmetrically-Blocked Architecture -- 64 128-Kbyte Erase Blocks (64 M) -- 32 128-Kbyte Erase Blocks (32 M) 4.5 V-5.5 V VCC Operation -- 2.7 V-3.6 V and 4.5 V-5.5 V I/O Capable 120 ns Read Access Time (32 M) 150 ns Read Access Time (64 M) Enhanced Data Protection Features -- Absolute Protection with VPEN = GND -- Flexible Block Locking -- Block Erase/Program Lockout during Power Transitions Industry-Standard Packaging -- SSOP Package (32, 64 M) TSOP Package (32 M) BGA* Package (64 M)
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Cross-Compatible Command Support -- Intel Basic Command Set -- Common Flash Interface -- Scalable Command Set 32-Byte Write Buffer -- 6 s per Byte Effective Programming Time 6,400,000 Total Erase Cycles (64 M) 3,200,000 Total Erase Cycles (32 M) -- 100,000 Erase Cycles per Block Automation Suspend Options -- Block Erase Suspend to Read -- Block Erase Suspend to Program System Performance Enhancements -- STS Status Output Operating Temperature -20 C to +85 C
Capitalizing on two-bit-per-cell technology, 5 Volt Intel(R) StrataFlashTM memory products provide 2X the bits in 1X the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel's 0.4 micron ETOXTM V process technology and Intel's 0x25 micron ETOX VI process technology, 5 Volt Intel StrataFlash memory provides the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290606-013 June 2000
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F320J5 and 28F640J5 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation 1997-2000. *Other brands and names are the property of their respective owners.
Preliminary
28F320J5 and 28F640J5
Contents
1.0 2.0 3.0 Product Overview.......................................................................................................1 Principles of Operation............................................................................................6
2.1 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Data Protection...................................................................................................... 6 Read...................................................................................................................... 8 Output Disable....................................................................................................... 8 Standby ................................................................................................................. 8 Reset/Power-Down ............................................................................................... 8 Read Query ........................................................................................................... 9 Read Identifier Codes............................................................................................ 9 Write ....................................................................................................................11 Read Array Command.........................................................................................13 Read Query Mode Command .............................................................................13 4.2.1 Query Structure Output ..........................................................................14 4.2.2 Query Structure Overview ......................................................................15 4.2.3 Block Status Register .............................................................................16 4.2.4 CFI Query Identification String ...............................................................16 4.2.5 System Interface Information .................................................................17 4.2.6 Device Geometry Definition....................................................................18 4.2.7 Primary-Vendor Specific Extended Query Table....................................18 Read Identifier Codes Command ........................................................................19 Read Status Register Command.........................................................................20 Clear Status Register Command.........................................................................20 Block Erase Command........................................................................................21 Block Erase Suspend Command ........................................................................21 Write to Buffer Command....................................................................................22 Byte/Word Program Commands .........................................................................22 Configuration Command .....................................................................................23 Set Block and Master Lock-Bit Commands.........................................................23 Clear Block Lock-Bits Command.........................................................................24 Three-Line Output Control...................................................................................33 STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................33 Power Supply Decoupling ...................................................................................33 Input Signal Transitions - Reducing Overshoots and Undershoots When Using Buffers/Transceivers.......................................................................34 VCC, VPEN, RP# Transitions ................................................................................34 Power-Up/Down Protection .................................................................................34 Power Dissipation................................................................................................35
Bus Operation..............................................................................................................7
4.0
Command Definitions.............................................................................................12
4.1 4.2
4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12
5.0
Design Considerations ..........................................................................................33
5.1 5.2 5.3 5.4 5.5 5.6 5.7
Preliminary
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6.0
Electrical Specifications........................................................................................ 35
6.1 6.2 6.3 6.4 6.5 6.6 6.7 Absolute Maximum Ratings ................................................................................ 35 Operating Conditions .......................................................................................... 35 Capacitance ........................................................................................................ 36 DC Characteristics .............................................................................................. 36 AC Characteristics--Read-Only Operations ....................................................... 39 AC Characteristics-- Write Operations............................................................... 41 Block Erase, Program, and Lock-Bit Configuration Performance ....................... 44
7.0 8.0
Ordering Information.............................................................................................. 45 Additional Information ........................................................................................... 46
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28F320J5 and 28F640J5
Revision History
Date of Revision 09/01/97 09/17/97 12/01/97 Version -001 -002 -003 Original version Modifications made to cover sheet Description
VCC/GND Pins Converted to No Connects Specification Change added ICCS, ICCD, ICCW and ICCE Specification Change added Order Codes Specification Change added
The BGA* chip-scale package in Figure 2 was changed to a 52-ball package and appropriate documentation added. The 64-Mb BGA package dimensions were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP. 32-Mbit Intel StrataFlash memory read access time added. The number of block erase cycles was changed. The write buffer program time was changed. The operating temperature was changed. A read parameter was added. Several program, erase, and lock-bit specifications were changed. Minor documentation changes were made as well. Datasheet designation changed from Advance Information to Preliminary. Intel StrataFlash memory 32-Mbit BGA package removed. tEHEL read specification reduced. Table 4 was modified. The Ordering Information was updated. Removed 32 Mbit, 100 ns references and ordering information for same. Provided clearer VOH specifications. Provided maximum program/erase specification. Added Input Signal Transitions--Reducing Overshoots and Undershoots When Using Buffers/Transceivers to Design Considerations section. Name of document changed from Intel(R) StrataFlashTM Memory Technology 32 and 64 Mbit. Updated CFI Tables, Section 4.2.1--Section 4.2.7. Operating Temperature Range Specification was increased to -20 C to +85 C. The 32-Mbit Read Access at +85 C was changed (Section 6.5, AC Characteristics-Read Only Operations). Modified Write Pulse Width definition Added lock-bit default status (Section 4.11) Added order code information for -20 C to +85 C Modified Chip Enable Truth Table Corrected error in command table Removed erase queuing option from Figure 9, Block Erase Flowchart Add reference to 0.25 micron process on cover page Corrected error in Table 10, Maximum buffer write time. Updated section 6.7 program/erase times. Corrected error in table 19 maximum temperature range
01/31/98
-004
03/23/98
-005
07/13/98 12/01/98
-006 -007
05/04/99 09/16/99
-008 -009
10/20/99
-010
11/08/99 12/16/99 06/26/00
-011 -012 -013
Preliminary
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28F320J5 and 28F640J5
1.0
Product Overview
The Intel(R) StrataFlashTM memory family contains high-density memories organized as 8 Mbytes or 4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase blocks while the 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. See the memory map in Figure 5 on page 7. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second-- independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance by up to 20 times over non-Write Buffer writes. Individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and program operations while the master lockbit gates block lock-bit modification. Three lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands). The status register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), or the device is in reset/power-down mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases.
Preliminary
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28F320J5 and 28F640J5
Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2, "Chip Enable Truth Table" on page 7) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1. When the device is disabled (see Table 2 on page 7) and the RP# pin is at VCC, the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The Intel StrataFlash memory devices are available in several package types. The 64-Mbit is available in 56-lead SSOP (Shrink Small Outline Package) and BGA* package (micro Ball Grid Array). The 32-Mbit is available in 56-lead TSOP (Thin Small Outline Package) and 56-lead SSOP. Figures 2, 3, and 4 show the pinouts.
Figure 1. Intel(R) StrataFlashTM Memory Block Diagram
DQ0 - DQ15
VCCQ
Output Buffer
Input Buffer
Query Output Multiplexer Write Buffer Data Register
I/O Logic CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Identifier Register Status Register
Command User Interface
Multiplexer Data Comparator
32-Mbit: A0- A21 64-Mbit: A0 - A22
Y-Decoder Input Buffer
Y-Gating Write State Machine 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Kbyte Blocks Program/Erase Voltage Switch
STS VPEN VCC GND
Address Latch Address Counter
X-Decoder
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28F320J5 and 28F640J5
Table 1.
Symbol A0
Lead Descriptions
Type INPUT Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A0-A21 64-Mbit: A0-A22 LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ6-DQ0 are also floated when the Write State Machine (WSM) is busy. Check SR.7 (status register bit 7) to determine WSM status. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CHIP ENABLES: Activates the device's control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 2 on page 7, power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. RP# at VHH enables master lock-bit setting and block lock-bits configuration when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enabling block erase and programming operations to locked memory blocks. Do not permanently connect RP# to VHH. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. STATUS: Indicates the status of the internal state machine. When configured in level mode (default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ0-DQ7, while DQ8-DQ15 float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN VPENLK, memory contents cannot be altered. SUPPLY OUTPUT BUFFER SUPPLY SUPPLY DEVICE POWER SUPPLY: With VCC VLKO, all write attempts to the flash memory are inhibited. OUTPUT BUFFER POWER SUPPLY: This voltage controls the device's output voltages. To obtain output voltages compatible with system data bus voltages, connect VCCQ to the system supply voltage. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
A1-A22
INPUT
DQ0-DQ7
INPUT/ OUTPUT
DQ8-DQ15
INPUT/ OUTPUT
CE0, CE1, CE2
INPUT
RP#
INPUT
OE# WE#
INPUT INPUT OPEN DRAIN OUTPUT
STS
BYTE#
INPUT
VPEN VCC VCCQ GND NC
INPUT
Preliminary
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28F320J5 and 28F640J5
Figure 2. BGA* Package (64 Mbit)
8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8
A
GND A10 VPEN CE0 A14 VCC VCC A14 CE0 VPEN A10 GND
A
B
A4 A7 A9 A11 A12 A15 A17 A19 A19 A17 A15 A12 A11 A9 A7 A4
B C
A5 A6 A8 RP# A13 A16 A21 A20 A20 A21 A16 A13 RP# A8 A6 A5
C
D
A2 A1 A3 A18 CE1 A22 A22 CE1 A18 A3 A1 A2
D E F
CE2 NC(1) BYTE# DQ7 NC(1) WE# WE# NC(1) DQ7 BYTE# NC(1) CE2
E F
G
A0 DQ8 DQ1 DQ3 DQ12 DQ6 DQ15 OE# OE# DQ15 DQ6 DQ12 DQ3 DQ1 DQ8
A0
G
H
DQ0 DQ9 DQ2 DQ11 DQ4 DQ13 DQ14 STS STS DQ14 DQ13 DQ4 DQ11 DQ2 DQ9
DQ0
H
I
VCC(1) DQ10 GND VCCQ DQ5 GND(1) GND(1) DQ5 VCCQ GND DQ10 VCC(1)
I
Bottom View - Ball Side Up
Top View
64-Mbit Intel(R) StrataFlashTM Memory: 7.67 mm x 16.37 mm NOTE: 1. VCC (Ball I7), GND (Ball I2), and NC (Balls F2 and F7) have been removed. Future generations of Intel StrataFlash memory may make use of these missing ball locations. Figures are not drawn to scale.
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28F320J5 and 28F640J5
Figure 3. TSOP Lead Configuration (32 Mbit)
28F160S5 28F016SV 28F032SA 28F320J5 28F016SA NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 CE2 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 NC CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28F320J5 28F032SA 28F016SV 28F160S5 28F016SA NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
Intel(R) StrataFlashTM Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
Highlights pinout changes
NOTES: 1. VCC (Pin 37) and GND (Pin 48) are not internally connected. For future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., Pin 37 = VCC and Pin 48 = GND). 2. For compatibility with future generations of Intel(R) StrataFlashTM memory, this NC (pin 56) should be connected to GND.
Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit)
28F016SA 28F160S5 28F320S5 28F016SV CE0# A12 A13 A14 A15 3/5# CE1# NC A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC CE0# A12 A13 A14 A15 NC CE1# NC A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC CE0# A12 A13 A14 A15 NC CE1# A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC 28F640J5 CE0 A12 A13 A14 A15 A22 CE1 A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 STS OE# WE# NC DQ13 DQ5 DQ12 DQ4 VCCQ 28F320J5 CE0 A12 A13 A14 A15 NC CE1 A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 STS OE# WE# NC DQ13 DQ5 DQ12 DQ4 VCCQ 1 2 3 4 5 6 7 8 9 10 Intel(R) 11 12 StrataFlashTM Memory 56-Lead SSOP 13 Standard Pinout 14 15 16 mm x 23.7 mm 16 17 Top View 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28F320J5 VPEN RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 DQ2 DQ10 DQ3 DQ11 GND 28F640J5 28F320S5 28F160S5 28F016SA 28F016SV VPEN RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND
Highlights pinout changes.
NOTES: 1. VCC (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., Pin 42 = VCC and Pin 15 = GND). 2. For compatibility with future generations of Intel(R) StrataFlashTM memory, this NC (pin 23) should be connected to GND.
Preliminary
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28F320J5 and 28F640J5
2.0
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset/power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allows array read, standby, and output disable operations. Read array, status register, query, and identifier codes can be accessed through the CUI (Command User Interface) independent of the VPEN voltage. VPENH on VPEN enables successful block erasure, programming, and lock-bit configuration. All functions associated with altering memory contents--block erase, program, lock-bit configuration--are accessed via the CUI and verified through the status register. Commands are written using standard micro-processor write timings. The CUI contents serve as input to the WSM, which controls the block erase, program, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during program cycles. Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or program data from/to any other block.
2.1
Data Protection
Depending on the application, the system designer may choose to make the VPEN switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to VPENH. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPEN VPENLK, memory contents cannot be altered. The CUI's two-step block erase, byte/ word program, and lock-bit configuration command sequences provide protection from unwanted operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is VIL. The device's block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations.
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28F320J5 and 28F640J5
3.0
Bus Operation
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Figure 5. Memory Map
A [22-0]: 64-Mbit A [21-0]: 32-Mbit
7FFFFF
A [22-1]: 64-Mbit A [21-1]: 32-Mbit
3FFFFF
128-Kbyte Block
7E0000
63 3F0000
64-Kword Block
63
128-Kbyte Block
3E0000
31 1F0000
64-Kword Block
31
03FFFF
01FFFF
128-Kbyte Block
020000 01FFFF
1 010000 00FFFF 0 000000
64-Kword Block 64-Kword Block
1 0
128-Kbyte Block
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table 2.
Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTES: 1. See Application Note, AP-647 5 Volt Intel(R) StrataFlashTM Memory Design Guide for typical CE configurations. 2. For single-chip applications CE2 and CE1 can be strapped to GND.
Preliminary
32-Mbit
64-Mbit
3FFFFF
1FFFFF
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28F320J5 and 28F640J5
3.1
Read
Information can be read from any block, query, identifier codes, or status register independent of the VPEN voltage. RP# can be at either VIH or VHH. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 2), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 2), select the memory device. OE# is the data output (DQ0-DQ15) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at VIH.
3.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
3.3
Standby
CE0, CE1, and CE2 can disable the device (see Table 2) and place it in standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs are placed in a highimpedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
3.4
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of t PLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
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28F320J5 and 28F640J5
flash memory may be providing status information instead of array data. Intel(R) Flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5
Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information, and Intel-specific extended query information.
3.6
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see Figure 6). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting.
Preliminary
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28F320J5 and 28F640J5
Figure 6. Device Identifier Code Memory Map
Word Address 3FFFFF A[22-1]: 64 Mbit A[21-1]: 32 Mbit Block 63 Reserved for Future Implementation Block 63 Lock Configuration Reserved for Future Implementation (Blocks 32 through 62) Block 31 Reserved for Future Implementation 1F0003 1F0002 Block 31 Lock Configuration 64 Mbit 32 Mbit Reserved for Future Implementation (Blocks 2 through 30) Block 1 Reserved for Future Implementation Block 1 Lock Configuration Reserved for Future Implementation Block 0 Reserved for Future Implementation Master Lock Configuration Block 0 Lock Configuration Device Code Manufacturer Code
3F0003 3F0002
3F0000 3EFFFF
1F0000 1EFFFF 01FFFF
010003 010002
010000 00FFFF
000004 000003 000002 000001 000000
NOTE: A0 is not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in x16 mode (upper byte contains 00h).
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3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block LockBits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on page 7). Standard microprocessor write timings are used.
Table 3.
Mode Read Array Output Disable Standby Reset/PowerDown Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM on) Write
Bus Operations
Notes 4,5,6 RP# VIH or VHH VIH or VHH VIH or VHH VIL VIH or VHH VIH or VHH VIH or VHH VIH or VHH 6,10,11 VIH or VHH CE0,1,2(1) Enabled Enabled Disabled X Enabled Enabled Enabled Enabled Enabled OE#(2) VIL VIH X X VIL VIL VIL VIL VIH WE#(2) VIH VIH X X VIH VIH VIH VIH VIL Address X X X X See Figure 6 See Table 7 X X X VPEN X X X X X X X VPENH X DQ(3) DOUT High Z High Z High Z Note 8 Note 9 DOUT DQ7 = DOUT DQ15-8 = High Z DQ6-0 = High Z DIN X STS (default mode) High Z(7) X X High Z(7) High Z(7) High Z(7)
NOTES: 1. See Table 2 for valid CE configurations. 2. OE# and WE# should never be enabled simultaneously. 3. DQ refers to DQ0-DQ7 if BYTE# is low and DQ0-DQ15 if BYTE# is high. 4. Refer to DC Characteristics. When VPEN VPENLK, memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), or reset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Read Identifier Codes Command section for read identifier code data. 9. See Read Query Mode Command section for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC is within specification. Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. 11. Refer to Table 4 for valid DIN during a write operation.
Preliminary
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4.0
Command Definitions
When the VPEN voltage VPENLK, only read operations from the status register, query, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.
Table 4.
Command
Intel(R) StrataFlashTM Memory Command Set Definitions(1,2)
Scaleable or Basic Command Set(2) Bus Cycles Req'd. Notes First Bus Cycle Second Bus Cycle
Oper(3) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write to Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Set Read Configuration Set Block LockBit Clear Block Lock-Bits Protection Program SCS SCS SCS/BCS SCS/BCS SCS SCS/BCS SCS/BCS SCS/BCS 1 2 2 2 1 >2 9, 10, 11 12,13 11,12 12,14 8 7 Write Write Write Write Write Write
Addr(4) X X X X X BA
Data(5,6) FFH 90H 98H 70H 50H E8H 40H or 10H 20H B0H
Oper(3)
Addr(4)
Data(5,6)
Read Read Read
IA QA X
ID QD SRD
Write
BA
N
SCS/BCS SCS/BCS SCS/BCS
2 2 1
Write Write Write
X X X
Write Write
PA BA
PD D0H
SCS/BCS SCS
1 2 2 2 2 2
12
Write Write Write Write
X X X X X X
D0H B8H 60H 60H 60H C0H Write Write Write Write Write X RCD BA X PA CC 03H 01H D0H PD
15
Write Write
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. If the WSM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 float, which places them in a highimpedance state.
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3. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. 4. Bus operations are defined in Table 3. 5. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 6 and Table 13. QA = Query database Address. PA = Address of memory location to be programmed. 6. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 7. The upper byte of the data bus (DQ8-DQ15) during command writes is a "Don't Care" in x16 operation. 8. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Read Identifier Codes Command section for read identifier code data. 9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 7, "Write to Buffer Flowchart" on page 27, for additional information. 11. Programming the write buffer to flash or initiating the erase operation does not begin until a confirm command (D0h) is issued. 12.If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or program to a locked block while RP# is VIH will fail. 13.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 14.If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 15.If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
4.1
Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend command. The Read Array command functions independently of the VPEN voltage and RP# can be VIH or VHH.
4.2
Read Query Mode Command
This section defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
Preliminary
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28F320J5 and 28F640J5
4.2.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-DQ7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-DQ7) and 00h in the high byte (DQ8-DQ15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 5.
Summary of Query Structure Output as a Function of Device and Mode
Device Type/ Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset x16 device x16 mode x16 device x8 mode 10h 10: 11: 12: Hex Code 0051 0052 0059 N/A(1 ASCII Value "Q" "R" "Y" Query data with byte addressing Hex Offset 20: 21: 22: 20: 21: 22: Hex Code 51 00 52 51 51 52 ASCII Value "Q" "Null" "R" "Q" "Q" "R"
N/A(1)
NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices.
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Table 6.
Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51 51 52 52 59 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "Q" "R" "R" "Y" "Y" PrVendor ID # ID # ... Value
4.2.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail.
Table 7.
Query Structure(1)
Offset 00h 01h (BA+2)h 10h 1Bh 27h
(2)
Sub-Section Name Manufacturer Code Device Code Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table
Description
Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm
04-0Fh
P
(3)
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.
Preliminary
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4.2.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block.
Table 8.
Block Status Register
Offset (BA+2)h(1) Length 1 Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR.1 Block Erase Status 0 = Last erase operation completed successfully 1 = Last erase operation did not complete successfully BSR 2-7: Reserved for Future Use Address BA+2: BA+2: Value --00 or --01 (bit 0): 0 or 1
BA+2: BA+2:
(bit 1): 0 or 1 (bit 2-7): 0
NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location in word mode).
4.2.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 9.
CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Add. 10 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: Hex Code --51 --52 --59 --01 --00 --31 --00 --00 --00 --00 --00 Value "Q" "R" "Y"
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
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4.2.5
System Interface Information
The following device information can optimize system interface software.
Table 10. System Interface Information
Offset Length Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2 ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2 times typical "n" such that maximum chip erase time-out = 2n times typical
n n
Add.
Hex Code --45
Value
1Bh
1
1B:
4.5 V
1Ch
1
1C:
--55
5.5 V
1Dh
1
1D:
--00
0.0 V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1 1
1E: 1F: 20: 21: 22: 23: 24: 25: 26:
--00 --07 --07 --0A --00 --04 --04 --04 --00
0.0 V 128 s 128 s 1s NA 2 ms 2 ms 16 s NA
Preliminary
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4.2.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 11. Device Geometry Definition
Offset 27h 28h Length 1 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 2Ah 2 "n" such that maximum number of bytes in write buffer = 2
n
Code See Table Below 27: 28: 29: 2A: 2B: --02 --00 --05 --00 32 x8/ x16
2Ch
1
Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes
2C:
--01
1
2Dh
4
2D: 2E: 2F: 30:
Table 12. Device Geometry Definition
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 32 Mbit --16 --02 --00 --05 --00 --01 --1F --00 --00 --02 64 Mbit --17 --02 --00 --05 --00 --01 --3F --00 --00 --02 128 Mbit (Info Only --18 --02 --00 --05 --00 --01 --7F --00 --00 --02
4.2.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information.
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Table 13. Primary Vendor-Specific Extended Query
Offset(1) P = 31h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length 3 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Reserved for Future Use Add. 31: 32: 33: 34: 35: 36: 37: 38: 39: bit 0 = 0 bit 1 = 1 bit 2 = 0 bit 3 = 1 bit 4 = 0 3A: bit 0 = 1 3B: 3C: bit 0 = 1 bit 1 = 0 3D: Hex Code --50 --52 --49 --31 --31 --0A --00 --00 --00 No Yes No Yes No --01 Yes --01 --00 Yes No --50 5.0 V Value "P" "R" "I" "1" "1"
1 1 4
(P+9)h
1
(P+A)h (P+B)h
2
(P+C)h
1
(P+D)h (P+E)h
1
3E: 3F:
--00
0.0 V
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
4.3
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 6 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Table 13 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPEN voltage and RP# can be VIH or VHH. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read:
Preliminary
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28F320J5 and 28F640J5
Table 14. Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit Block Lock Configuration * Block Is Unlocked * Block Is Locked * Reserved for Future Use Master Lock Configuration * Device Is Unlocked * Device Is Locked * Reserved for Future Use 00003 DQ0 = 0 DQ0 = 1 DQ1-7 Address(1) 00000 00001 00001
X0002(2)
Data (00) 89 (00) 14 (00) 15 DQ0 = 0 DQ0 = 1 DQ1-7
NOTES: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block's lock configuration code. See Figure 6 for the device identifier code memory map.
4.4
Read Status Register Command
The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 2). OE# must toggle to VIH or the device must be disabled (Table 2) before further reads to update the status register latch. The Read Status Register command functions independently of the VPEN voltage. RP# can be VIH or VHH. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid until the WSM completes or suspends the operation. Device I/O pins DQ0-DQ6 and DQ8-DQ15 are placed in a high-impedance state. When the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read.
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 16). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPEN voltage. RP# can be VIH or VHH. The Clear Status Register command is only valid when the WSM is off or the device is suspended.
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4.6
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 9, "Block Erase Flowchart" on page 29). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to update the status register. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1." Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. If block erase is attempted while VPEN VPENLK, SR.3 and SR.5 will be set to "1." Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to "1." Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.7
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). In default mode, STS will also transition to VOH. Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to "0" and the STS output (in default mode) will transition to VOL. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10, "Block Erase Suspend/Resume Flowchart" on page 30). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
Preliminary
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4.8
Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer setup command is issued along with the Block Address (see Figure 7, "Write to Buffer Flowchart" on page 27). At this point, the eXtended Status Register (XSR, see Table 17, "Status Register Definition" on page 26) information is loaded and XSR.7 reverts to "buffer available" status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a "1," the buffer is ready for loading. Now a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A4-A0 of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated and status register bits SR.5 and SR.4 will be set to a "1." For additional buffer writes, issue another Write to Buffer setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set to a "1" to indicate a program failure. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. If a program error is detected, the status register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an "Invalid Command/Sequence" error and status register bits SR.5 and SR.4 will be set to a "1." Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted while VPEN VPENLK, status register bits SR.4 and SR.3 will be set to "1." Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding Block Lock-Bit be reset or, if set, that RP# = VHH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1." Buffered write operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.9
Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, "Byte/Word Program Flowchart" on page 28). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7.
22
Preliminary
28F320J5 and 28F640J5
When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN VPENLK, status register bits SR.4 and SR.3 will be set to "1." Successful byte/word programs require that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If a byte/word program is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to "1." Byte/word program operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.10
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 15, "Write Protection Alternatives" on page 25 displays the possible STS configurations. To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. The possible configurations and their usage are described in Table 15. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to "1." When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
4.11
Set Block and Master Lock-Bit Commands
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. Out of the factory, the block lock-bits and the master lock-bit are unlocked. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. These commands are invalid while the WSM is running or the device is suspended. See Table 14, "Identifier Codes" on page 20 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit commands are executed by a two-cycle sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11, "Set Block Lock-Bit Flowchart" on page 31). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7.
Preliminary
23
28F320J5 and 28F640J5
When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to "1." Also, reliable operations occur only when VCC and VPEN are valid. With VPEN VPENLK, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to "1" and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.12
Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block LockBits command and VHH on the RP# pin. This command is invalid while the WSM is running or the device is suspended. See Table 14, "Identifier Codes" on page 20 for a summary of hardware and software write protection options. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs status register data when read (see Figure 12, "Clear Block Lock-Bit Flowchart" on page 32). The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to "1." Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN VPENLK, SR.3 and SR.5 will be set to "1." A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to "1" and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared.
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Preliminary
28F320J5 and 28F640J5
Table 15. Write Protection Alternatives
Operation Block Erase or Program X Master Lock-Bit Block Lock-Bit 0 1 RP# VIH or VHH VIH VHH Set or Clear Block Lock-Bits 0 1 X X VIH or VHH VIH VHH Set Master Lock-Bit X X VIH VHH Effect Block Erase and Program Enabled Block is Locked. Block Erase and Program Disabled Block Lock-Bit Override. Block Erase and Program Enabled Set or Clear Block Lock-Bit Enabled Master Lock-Bit Is Set. Set or Clear Block Lock-Bit Disabled Master Lock-Bit Override. Set or Clear Block Lock-Bit Enabled Set Master Lock-Bit Disabled Set Master Lock-Bit Enabled
Table 16. Configuration Coding Definitions
Reserved Pulse on Program Complete(1) Bit 1 DQ7-DQ2 are reserved for future use. default (DQ1-DQ0 = 00) RY/BY#, level mode -- used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. configuration 01 ER INT, pulse mode -- used to generate a system interrupt pulse when any flash device in an array has completed a Block Erase or sequence of Queued Block Erases. Helpful for reformatting blocks after file system free space reclamation or "cleanup" configuration 10 PR INT, pulse mode -- used to generate a system interrupt pulse when any flash device in an array has complete a Program operation. Provides highest performance for servicing continuous buffer write operations. configuration 11 ER/PR INT, pulse mode -- used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed when a common interrupt service routine is desired. Pulse on Erase Complete(1) Bit 0
Bits 7--2 DQ7-DQ2 = Reserved DQ1-DQ0 = STS Pin Configuration Codes 00 = default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = pulse on Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b, 10b, and 11b are all pulse mode such that the STS pin pulses low then high when the operation indicated by the given configuration is completed. Configuration Command Sequences for STS pin configuration (masking bits DQ7-DQ2 to 00h) are as follows: Default RY/BY# level mode: B8h, 00h ER INT (Erase Interrupt): B8h, 01h Pulse-on-Erase Complete PR INT (Program Interrupt): B8h, 02h Pulse-on-Program Complete ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete
NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
Preliminary
25
28F320J5 and 28F640J5
Table 17. Status Register Definition
WSMS bit 7 High Z When Busy? No ESS bit 6 ECLBS bit 5 PSLBS bit 4 VPENS bit 3 R bit 2 DPS bit 1 Notes Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not driven while SR.7 = "0." If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block/Master Lock-Bit, or Clear Block Lock-Bits command sequences. SR.1 does not provide a continuous indication of master and block lock-bit values. The WSM interrogates the master lock-bit, block lock-bit, and RP# only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or RP# is not VHH. Read the block lock and master lock configuration codes using the Read Identifier Codes command to determine master and block lock-bit status. SR.2 and SR.0 are reserved for future use and should be masked when polling the status register. R bit 0
Status Register Bits SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in Programming or Set Master/Block Lock-Bit 0 = Successful Programming or Set Master/Block Lock Bit SR.3 = PROGRAMMING VOLTAGE STATUS 1 = Low Programming Voltage Detected, Operation Aborted 0 = Programming Voltage OK SR.2 = RESERVED FOR FUTURE ENHANCEMENTS SR.1 = DEVICE PROTECT STATUS 1 = Master Lock-Bit, Block Lock-Bit and/or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Yes
Yes
Yes
Yes
Yes Yes
Yes
Table 18. eXtended Status Register Definition
WBS bit 7 High Z When Busy? No Status Register Bits XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available XSR.6-XSR.0 = RESERVED FOR FUTURE ENHANCEMENTS Reserved bits 6--0 Notes After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available. SR.6-SR.0 are reserved for future use and should be masked when polling the status register.
Yes
26
Preliminary
28F320J5 and 28F640J5
Figure 7. Write to Buffer Flowchart
Start Set Time-Out Issue Write to Buffer Command E8H, Block Address Read Extended Status Register No Bus Operation Write Read
Command Write to Buffer
Comments Data = E8H Block Address XSR. 7 = Valid Addr = Block Address Check XSR. 7 1 = Write Buffer Available 0 = Write Buffer Not Available Data = N = Word/Byte Count N = 0 Corresponds to Count = 1 Addr = Block Address Data = Write Buffer Data Addr = Device Start Address Data = Write Buffer Data Addr = Device Address
Standby
XSR.7 = 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address X=0 Yes Check X = N? No Abort Write to Buffer Command? Yes No Write Next Buffer Data, Device Address X=X+1 Program Buffer to Flash Confirm D0H
0
Write to Buffer Time-Out?
Write (Note 1, 2) Write (Note 3, 4) Write (Note 5, 6) Write
Program Buffer Data = D0H to Flash Addr = Block Address Confirm Status Register Data with the Device Enabled, OE# Low Updates SR Addr = Block Address Check SR.7 1 = WSM Ready 0 = WSM Busy
Read (Note 7)
Standby Yes Yes Write to Another Block Address
Write to Buffer Aborted
1. Byte or word count values on DQ - DQ7 are loaded into the 0 count register. Count ranges on this device for byte mode are N = 00H to 1FH and for word mode are N = 0000H to 000FH. 2. The device now outputs the status register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A - A0 of the start 4 address = 0). 5. The device aborts the Write to Buffer command if the current address is outside of the original block address. 6. The status register indicates an "improper command sequence" if the Write to Buffer command is aborted. Follow this with a Clear Status Register command. 7. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode.
Another Write to Buffer? No Read Status Register 1 0 SR.7 = 1 Full Status Check if Desired Programming Complete Issue Read Status Command
0606_07
Preliminary
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28F320J5 and 28F640J5
Figure 8. Byte/Word Program Flowchart
Start
Bus Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data = 40H Addr = Location to Be Programmed Data = Data to Be Programmed Addr = Location to Be Programmed Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address Write Data and Address Read Status Register 0
Read (Note 1) Standby
SR.7 = 1 Full Status Check if Desired Byte/Word Program Complete
1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming to Voltage Error Detect Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Check SR.4 1 = Programming Error
1 Device Protect Error
Standby
Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
0606_08
28
Preliminary
28F320J5 and 28F640J5
Figure 9. Block Erase Flowchart
Bus Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note 1)
Start
Command Erase Block Erase Confirm
Comments Data = 20H Addr = Block Address Data = D0H Addr = X Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy
Read
Standby Write Confirm D0H Block Address
1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Suspend Erase Loop
Read Status Register No
SR.7 =
0
Suspend Erase
Yes
1 Full Status Check if Desired
Erase Flash Block(s) Complete
0606_09
Preliminary
29
28F320J5 and 28F640J5
Figure 10. Block Erase Suspend/Resume Flowchart
Start
Bus Operation Write
Command Erase Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Write B0H Read
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.6 = Block Erase Completed
Erase Resume
Data = D0H Addr = X
1 Read Read or Program? Read Array Data Done? Yes Write D0H Write FFH Program Loop Program
No
Block Erase Resumed
Read Array Data
0606_10
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Preliminary
28F320J5 and 28F640J5
Figure 11. Set Block Lock-Bit Flowchart
Start
Bus Operation Write
Command Set Block/Master Lock-Bit Setup
Comments Data = 60H Addr =Block Address (Block), Device Address (Master) Data = 01H (Block) F1H (Master) Addr = Block Address (Block), Device Address (Master) Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address
Write
Set Block or Master Lock-Bit Confirm
Read Status Register
Read
Standby
SR.7 = 1 Full Status Check if Desired
0
Repeat for subsequent lock-bit operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR. 1 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful
0606_11
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.1 1 = Device Protect RP# = VIH (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit Is Set (set Block Lock-Bit Operation) Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
Voltage Range Error
Standby
1 Device Protect Error
Standby
Command Sequence Error
Standby
Set Lock-Bit Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Preliminary
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28F320J5 and 28F640J5
Figure 12. Clear Block Lock-Bit Flowchart
Start
Bus Operation Write
Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm
Comments Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H
Write
Write D0H
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired Clear Block Lock-Bits Complete
0
Write FFH after the clear lock-bits operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR. 1 = 0 1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful
0606_12
Bus Operation Standby
Command
Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.1 1 = Device Protect RP# = VIH, Master Lock-Bit Is Set Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
Voltage Range Error
Standby
1 Device Protect Error
Standby
Standby
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery.
Clear Block Lock-Bits Error
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Preliminary
28F320J5 and 28F640J5
5.0
5.1
Design Considerations
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
* Lowest possible memory power dissipation. * Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 2) while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2
STS and Block Erase, Program, and Lock-Bit Configuration Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS pin, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive) or in reset/power-down mode.
5.3
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three VCC pins (these devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1 F ceramic capacitor between each of the device's three VCC pins (this includes VCCQ) and ground. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each Intel StrataFlash memory device. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed between VCC and GND at the array's power supply connection. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
Preliminary
33
28F320J5 and 28F640J5
5.4
Input Signal Transitions - Reducing Overshoots and Undershoots When Using Buffers/Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications (see Section 6.1, Absolute Maximum Ratings). Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or lightdrive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When selecting a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be considered to minimize overshoots and undershoots. For additional information, please refer to AP-647, 5 Volt Intel(R) StrataFlashTM Memory Design Guide (order 292205).
5.5
VCC, VPEN, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# VIH or VHH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the status register. The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.
5.6
Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lockbit configuration during power transitions. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPEN is active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving WE# to VIH or disabling the device will inhibit writes. The CUI's two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled while RP# = VIL regardless of its control inputs.
34
Preliminary
28F320J5 and 28F640J5
5.7
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed.
6.0
6.1
Electrical Specifications
Absolute Maximum Ratings
Maximum Rating for Commercial Temperature Devices -20 C to +70 C -65 C to +125 C -2.0 V to +7.0 V(1) -2.0 V to +14.0 V(1,2,3) 100 mA(4) Maximum Rating for Extended Temperature Devices -20 C to +85 C -65 C to +125 C -2.0 V to +7.0 V(1) -2.0 V to +14.0 V(1,2,3) 100 mA(4)
Parameter Temperature under Bias Expanded Storage Temperature Voltage On Any Pin (except RP#) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations Output Short Circuit Current
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPEN pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins, VCC, and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on RP# may overshoot to +14.0 V for periods <20 ns. 3. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. 4. Output shorted for no more than one second. No more than one output shorted at a time.
NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
6.2
Operating Conditions
Table 19. Temperature and VCC Operating Conditions
Symbol TA VCC VCCQ1 VCCQ2 Parameter Operating Temperature VCC1 Supply Voltage (5 V 10%) VCCQ1 Supply Voltage (5 V 10%) VCCQ2 Supply Voltage (2.7 V --3.6 V) Notes Min -20 4.50 4.50 2.70 Max +85 5.50 5.50 3.60 Unit C V V V Test Condition Ambient Temperature
Preliminary
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28F320J5 and 28F640J5
6.3
Capacitance
TA = +25C, f = 1 MHz
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0 V VOUT = 0.0 V
NOTE: 1. Sampled, not 100% tested.
6.4
Symbol ILI ILO ICCS
DC Characteristics
Parameter Input and VPEN Load Current Output Leakage Current VCC Standby Current Notes 1 1 1,2,3 80 450 325 Typ Max 1 10 150 900 650 Unit A A A A A A Test Conditions VCC = VCC Max, VIN = VCC or GND VCC = VCC Max, VIN = VCC or GND CMOS Inputs, VCC = VCC Max, CE0 = CE1 = CE2 = RP# = VCCQ1 0.2 V CMOS Inputs, RP# = VCC = VCC Max, CE0 = CE1 = CE2 = VCCQ2 Min CMOS Inputs, RP# = VCC = VCC Max, CE2 = GND, CE0 = CE1 = VCCQ2 Min CMOS Inputs, RP# = VCC = VCC Max, CE1 = CE2 = GND, CE0 = VCCQ2 Min or CE0 = CE2 = GND, CE1 = VCCQ2 Min TTL Inputs, VCC = VCC Max, CE0 = CE1 = CE2 = RP# = VIH RP# = GND 0.2 V IOUT (STS) = 0 mA CMOS Inputs, VCC = VCCQ =VCC Max Device is enabled (see Table 2) f = 5 MHz IOUT = 0 mA TTL Inputs ,VCC = VCC Max Device is enabled (see Table 2) f = 5 MHz IOUT = 0 mA CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC Device is disabled (see Table 2)
210
400
0.71 ICCD VCC Power-Down Current 80
2 125
mA A
ICCR
VCC Read Current
1,3,4
35
55
mA
45
65
mA
ICCW
VCC Program or Set Lock-Bit Current
1,4,5
35 40
60 70 70 80 10
mA mA mA mA mA
ICCE
VCC Block Erase or Clear Block Lock-Bits Current
1,4,5
35 40
ICCES
VCC Block Erase Suspend Current
1,6
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Preliminary
28F320J5 and 28F640J5
DC Characteristics, Continued
Symbol VIL VIH VOL Parameter Input Low Voltage Input High Voltage Output Low Voltage Notes 5 5 2,5 Min -0.5 2.0 Max 0.8 VCC + 0.5 0.45 0.4 VOH Output High Voltage 3,7 2.4 Unit V V V V V VCCQ = VCCQ1 Min, IOL = 5.8 mA VCCQ = VCCQ2 Min, IOL = 2 mA VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = -2.5 mA (VCCQ1) -2 mA (VCCQ2) 0.85 X VCCQ VCCQ -0.4 VPENLK VPENH VLKO VHH VPEN Lockout during Normal Operations VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage RP# Unlock Voltage 5,7,8 7,8 9 10,11 3.6 4.5 3.25 11.4 12.6 5.5 V V V V V V Set master lock-bit Override lock-bit VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = -2.5 mA VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = -100 A Test Conditions
NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 4. Add 5 mA for VCCQ = VCCQ2 min. 5. Sampled, not 100% tested. 6. ICCES is specified with the device de-selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR or ICCW. 7. Tie VPEN to VCC (4.5 V-5.5 V). 8. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 9. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 10.Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and programming are inhibited when the corresponding block-lock bit is set and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with VIH < RP# < VHH. 11. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
Preliminary
37
28F320J5 and 28F640J5
Figure 13. Transient Input/Output Reference Waveform for VCCQ = 5.0 V 10% (Standard Testing Configuration)
2.4 Input 0.45
2.0 Test Points 0.8
2.0 Output 0.8
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform
2.7 Input 0.0 1.35 Test Points 1.35 Output
NOTE: AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends,
at 1.35 V (50% of VCCQ). Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Equivelent Testing Load Circuit
1.3V 1N914 RL = 3.3 k Device Under Test Out CL
NOTE: CL Includes Jig Capacitance
Table 20. Test Configuration Capacitance Loading Value
Test Configuration VCCQ = 5.0 V 10% VCCQ = 2.7 V-3.6 V CL (pF) 100 50
38
Preliminary
28F320J5 and 28F640J5
6.5
AC Characteristics--Read-Only Operations(1)
Versions 5 V 10% VCCQ 2.7 V--10% VCCQ Notes 32 Mbit Min 120 130 at +85 C 150 120 130 at +85 C 150 3 3 3 32 Mbit 120 130 at +85 C 150 50 180 210 4 4 4 4 4 4 0 10 1000 4 4 10 1000 0 0 55 15 -120/-150(2) -120/-150(2) Max
(All units in ns unless otherwise noted) # Sym Parameter
R1
tAVAV
Read/Write Cycle Time 64 Mbit 32 Mbit
R2
tAVQV
Address to Output Delay 64 Mbit 32 Mbit
R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14
tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tELFL tELFH tFLQV tFHQV tFLQZ tEHEL
CEX to Output Delay 64 Mbit OE# to Output Delay RP# High to Output Delay 64 Mbit CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low BYTE# to Output Delay BYTE# to Output in High Z CEx Disable Pulse Width
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (seeTable 2). 1. See Figure 16, "AC Waveform for Read Operations" on page 40 for the maximum allowable input slew rate. 2. See Figure 13, Figure 14, and Figure 15 on page 38, for testing characteristics 3. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2) without impact on tELQV. 4. Sampled, not 100% tested.
Preliminary
39
28F320J5 and 28F640J5
Figure 16. AC Waveform for Read Operations
Standby VIH Device Address Selection Address Stable VIL R1 R14 Data Valid
ADDRESSES [A]
Disabled (VIH)
CEX [E]
Enabled (VIL) R2 R8 VIH VIL R3 R4 R5 High Z R6 Valid Output R7 R10 High Z R9
OE# [G]
WE# [W]
VIH VIL
DATA [D/Q] VOH DQ0-DQ15
VOL VIH VIL VIH
VCC
RP# [P]
VIL VIH
R11
R12 R13
BYTE# [F]
VIL
0606_16
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, "Chip Enable Truth Table" on page 7).
40
Preliminary
28F320J5 and 28F640J5
6.6
AC Characteristics-- Write Operations(1,2)
Valid for All Speeds Parameter RP# High Recovery to WE# (CEX ) Going Low CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX ) Going High Address Setup to WE# (CEX ) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX ) High Address Hold from WE# (CEX ) High Write Pulse Width High RP# VHH Setup to WE# (CEX ) Going High VPEN Setup to WE# (CEX ) Going High Write Recovery before Read WE# (CEX ) High to STS Going Low RP# VHH Hold from Valid SRD, STS Going High VPEN Hold from Valid SRD, STS Going High 6 3 3 7 8 3,8,9 3,8,9 0 0 Notes 3 4 4 5 5 Min 1 0 70 50 50 10 0 0 30 0 0 35 90 Max Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Versions # W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Sym tPHWL (tPHEL) tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tPHHWH (tPHHEH) tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVPH tQVVL
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on page 7). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 5. Refer to Table 4 on page 12 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH (and if necessary RP# should be held at VHH) until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
Preliminary
41
28F320J5 and 28F640J5
Figure 17. AC Waveform for Write Operations
A VIH VIL Disabled (V IH) CEX, (WE#) [E(W)] Enabled (V IL) VIH OE# [G] VIL
W2 W1
B
C
D
E
F
ADDRESSES [A]
AIN W5
AIN W8
W6
W12
W9
W16
Disabled (V IH) WE#, (CEX) [W(E)] Enabled (V IL)
W4
W3 W7 DIN DIN W13 Valid SRD DIN High Z
VIH DATA [D/Q] VIL VOH STS [R] VOL VHH VIH VIL
W10
W14
RP# [P]
W11
W15
VPENH VPENLK VPEN [V] VIL
0606_17
NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2 on page 7). STS is shown in its
default mode (RY/BY#).
a. b. c. d. e. f.
VCC power-up and standby. Write block erase, write buffer, or program setup. Write block erase or write buffer confirm, or valid address and data. Automated erase delay. Read status register or query data. Write Read Array command.
42
Preliminary
28F320J5 and 28F640J5
Figure 18. AC Waveform for Reset Operation
STS (R)
VIH VIL P2 VIH VIL P1
0606_18
RP# (P)
NOTE: STS is shown in its default mode (RY/BY#).
Table 21. Reset Specifications(1)
# P1 P2 Sym tPLPH tPHRH Parameter RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Notes 2 3 Min 35 100 Max
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
Preliminary
43
28F320J5 and 28F640J5
6.7
Block Erase, Program, and Lock-Bit Configuration Performance(1,2)
Sym Write Buffer Program Time tWHQV3 tEHQV3 Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) Parameter Notes 4,5,6,7 4 4 4 4 4 Typ(3) 218 210 0.8 1.0 64 .50 26 Max 654 630 2.4 5.0 75 .70 35 Unit s s sec sec s sec s
# W16 W16
W16 W16 W16 W16
tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH tEHRH
Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Erase Suspend Latency Time to Read
NOTES: 1. These performance numbers are valid for all speed versions. 2. Sampled but not 100% tested. 3. Typical values measured at TA = +25 C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 s/byte (typical). 7. Effective per-word program time (tWHQV2, tEHQV2) is 13.6 s/byte (typical).
44
Preliminary
28F320J5 and 28F640J5
7.0
Ordering Information
G2 8 F 6 4 0 J 5 - 1 5 0
Package G = 56-Ball BGA* CSP E = 56-Lead TSOP DA = 56-Lead SSOP DT = 56-Lead SSOP (-20 C to +85 C) Product line designator for all Intel(R) Flash products Device Density 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Access Speed (ns) 32 Mbit = 120 64 Mbit = 150
Voltage (VCC/VPEN) 5 = 5 V/5 V Product Family J = Intel(R) StrataFlashTM memory, 2 bits-per-cell
Order Code by Density 32 Mbit DA28F320J5-120 E28F320J5-120 DT28F320J5-120 64 Mbit DA28F640J5-150 DT28F640J5-150 G28F640J5-150
Valid Operational Conditions 5 V VCC 2.7 V - 3.6 V VCCQ Yes Yes Yes 5 V 10% VCCQ Yes Yes Yes
Preliminary
45
28F320J5 and 28F640J5
8.0
Additional Information
Order Number Contact Intel/Distribution Sales Office 290667 210830 290608 290609 290429 290598 290597 292235 297859 292222 292221 292218 292205 292204 292202 297846
(R)
Document/Tool
5 Volt Intel StrataFlashTM Memory 0.25 Generation/32-, and 64-Mbit Densities EAS 3 Volt Intel(R) StrataFlashTM Memory; 28F128J3A, 28F640J3A, 28F320J3A datasheet Flash Memory Databook 3 Volt FlashFileTM Memory; 28F160S3 and 28F320S3 datasheet 5 Volt FlashFileTM Memory; 28F160S5 and 28F320S5 datasheet 5 Volt FlashFileTM Memory; 28F008SA datasheet 3 Volt FlashFileTM Memory; 28F004S3, 28F008S3, 28F016S3 datasheet 5 Volt FlashFileTM Memory; 28F004S5, 28F008S5, 28F016S5 datasheet AP-687 5 Volt Intel(R) StrataFlashTM Memory Interface to the SA-1100 AP-677 Intel(R) StrataFlashTM Memory Technology AP-664 Designing Intel(R) StrataFlashTM Memory into Intel(R) Architecture AP-663 Using the Intel(R) StrataFlashTM Memory Write Buffer AP-660 Migration Guide to 3 Volt Intel(R) StrataFlashTM Memory AP-647 5 Volt Intel(R) StrataFlashTM Memory Design Guide AP-646 Common Flash Interface (CFI) and Command Sets AP-644 Migration Guide to 5 Volt Intel(R) StrataFlashTM Memory Comprehensive User's Guide for BGA* Packages
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. For the most current information on Intel StrataFlash memory, visit our website at http://developer.intel.com/ design/flash/isf.
46
Preliminary

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